Semiconductor integrated circuit and nonvolatile memory element

ABSTRACT

An information retention capability based on a memory cell which comprises a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data. A word line voltage in a readout mode is set to be substantially equal to a threshold voltage in a thermal equilibrium state (an initial threshold voltage), and also to be substantially equal to the average value of a low threshold voltage value and a high threshold voltage value. Thus, a data retention capability is enhanced to realize lowering in the rate of readout faults.

[0001] This application is a division of U.S. Application Serial No. 09/493,280, filed on Jan. 28, 2000, and incorporates by reference the same herein.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a semiconductor integrated circuit having electrically erasable and programmable nonvolatile memory elements. More particularly, the invention relates, for example, to techniques which are effective when applied to a semiconductor integrated circuit having a nonvolatile memory wherein two nonvolatile memory elements are used as a storage unit.

[0003] In recent years, as a memory device in which data or program-constituting data are stored, substantial public attention has been directed to a flash EEPROM (hereinbelow, termed “flash memory”), which is a nonvolatile storage device from/into which stored data/data to be stored are electrically erasable/programmable collectively in predetermined units. The flash memory has its memory cells configured of electrically erasable and programmable nonvolatile memory elements, and it is capable of erasing data or program-constituting data once written into the memory cells and rewriting (programming) new data or program-constituting data into the memory cells.

[0004] Therefore, for the purpose of, e.g., altering data, correcting the bugs of a program or updating a program after a flash memory or a macrocomputer having a built-in flash memory has been assembled into an application system, data or data constituting the program as stored in the flash memory can be altered, so that the term necessary for the development of the application system can be shortened, and so that the flexibility of the development of the program of the application system is enhanced.

[0005] On the other hand, in recent years, note has also been taken of a system semiconductor device (hereinbelow, also termed “system LSI”) wherein one system can be constructed of a single semiconductor integrated circuit device by forming on a single semiconductor substrate a central processing unit (hereinbelow, also termed “CPU”) as a data control device, a dynamic random access memory (hereinbelow, also termed “DRAM”) as a large-scale storage device, a static random access memory (hereinbelow, also termed “SRAM”) as a high-speed storage device or cache memory, and other fqoctional circuits. Such a system LSI is effective for reducing the size of a printed circuit board or packaging circuit board, etc., and especially for reducing the size and lightening the weight of a portable telephone set, a portable data terminal, and similar portable equipment.

[0006] Incidentally, after the completion of the present invention, the inventors investigated into known examples from a viewpoint-A and a viewpoint-B, as stated below.

[0007] The viewpoint-A concerns the use of a polysilicon gate of single layer for forming the memory cell of a nonvolatile memory, while the viewpoint-B concerns the use of two memory cells in a differential fashion.

[0008] As a result, regarding the viewpoint-A, there have been found the official gazette of U.S. Pat. No. 5,440,159, the official gazette of U.S. Pat. No. 5,504,706, the official gazette of Japanese Patent Application Laid-open No. 212471/1992 (the official gazette of corresponding U.S. Pat. No. 5,457,335), and Oosaki et al., “A single Ploy EEPROM Cell Structure for Use in Standard CMOS Processes”, IEEE Journal of solid sate circuits″, VOL. 29, NO. 3, March 1994, pp 311-316.

[0009] On the other hand, regarding the viewpoint-B, there have been found the official gazettes of Japanese Patent Applications Laid-open No. 163797/1992, No. 263999/1989, No. 74392/1992, No. 127478/1992, No. 129091/1992 and No. 268180/1994, and the official gazette of U.S. Pat. No. 5,029,131.

[0010] By the way, the official gazette of Japanese Patent Application Laid-open No. 212471/1992 discloses also a technique which utilizes an electrically programmable nonvolatile memory (EPROM) as a remedy circuit for a read only memory (ROM). Further, the official gazette contains the statement that the nonvolatile memory element of single-layer gate structure according to this invention can be utilized also as an electrically programmable and erasable nonvolatile memory element which executes programming with hot carriers and executes erasing with a tunneling current by applying a high voltage to a source or a drain, or which executes programming and erasing with tunneling currents.

SUMMARY OF THE INVENTION

[0011] The documents found by the investigation into the known examples have not disclosed at all the possibility that nonvolatile memory cells, each employing a single polysilicon layer may be utilized in a differential form, a discussion concerning the relationship between the initial threshold voltage of the memory cells (the threshold voltage in a thermal equilibrium state) and a word line potential in a data readout mode, in the case where the nonvolatile memory cells each employing the single polysilicon layer are utilized in the differential form, and so forth.

[0012] In addition, the following facts have been revealed by the inventors.

[0013] It has been found by the inventors that even a memory cell structure in the differential form has a first problem in that the occurring rate of readout faults ascribable to the deterioration of charge retention characteristics are greatly affected by the states of an initial threshold voltage under which no charge exists in a floating gate, threshold voltages in write and erase states, and a word line potential in a readout operation. Incidentally, FIGS. 12 and 13 to be referred to below do not belong to known techniques, but they are drawings created by the inventors in order to facilitate the understanding of the present invention.

[0014]FIG. 12 shows the threshold voltage distribution of memory cells in the case where the initial threshold voltage (Vthi) is set comparatively high. By way of example, the initial threshold voltage (Vthi) is set higher than the average value between a low threshold voltage (VthL) as in the erase state and a high threshold voltage (VthH) as in the write state. The readout word line potential (Vread) is set in the medium range between the low threshold voltage (VthL) and the initial threshold voltage (Vthi). In the set state, the voltage difference between the initial threshold voltage (Vthi) and the high threshold voltage (VthH) under which electrons are accumulated in the floating gate is small. That is, the quantity of accumulated charges is small, and a retaining field strength which is applied to a tunnel oxide film in a retention state is low. As a result, the fall of the threshold voltage attributed to charge leakage from the floating gate is difficult to develop. On the other hand, an electric field in the direction of injecting electrons into the floating gate is applied to the tunnel oxide film of the memory cell of the low threshold voltage (VthL) by the word line voltage in the readout operation, so that the rise of the threshold voltage or a so-called “charge gain” develops. On this occasion, the undesirable rise of the threshold voltage mounts up to the initial threshold voltage (Vthi), so that when the threshold voltage has become higher than the readout word line potential (Vread), data is inverted so as to produce a readout fault. It has accordingly been revealed by the inventors that the characteristics as shown in FIG. 12 are comparatively good at the data retention, but that they are less immune against the charge gain.

[0015] Contrariwise to the above, FIG. 13 shows the threshold voltage distribution of memory cells in the case where the initial threshold voltage (Vthi) is set comparatively low. By way of example, the initial threshold voltage (Vthi) is set lower than the average value between the low threshold voltage (VthL) and the high threshold voltage (VthH). The readout word line potential (Vread) is set in the medium range between the low threshold voltage (VthL) and the initial threshold voltage (Vthi). In the set state, the voltage difference between the initial threshold voltage (Vthi) and the low threshold voltage (VthL) under which electrons are not accumulated in the floating gate is small, and the charge gain based on the word line voltage in the readout operation is difficult to occur. On the other hand, the memory cell of the high threshold voltage (VthH) has a large voltage difference from the initial threshold voltage (Vthi), so that the quantity of accumulated charges is large, and so that the retaining field strength which is applied to the tunnel oxide film in the retention state is high. As a result, the undesirable fall of the threshold voltage attributed to the charge leakage from the floating gate is liable to develop. On this occasion, the undesirable fall of the threshold voltage mounts up to the initial threshold voltage (Vthi), so that when the threshold voltage has become lower than the readout word line potential (Vread), data is inverted so as to produce a readout fault. It has been found by the inventors that the characteristics as shown in FIG. 13 are immune against the charge gain and can produce a comparatively large readout current owing to the large difference between the low threshold voltage (VthL) and the readout word line potential (Vread), but that they are not good at the data retention.

[0016] As a second problem, there is also the problem that, with memory cells of a floating gate/control gate vertically-stacking structure, namely, memory cells of the stacked gate type, the manufacturing cost thereof increases due to the complicated memory cell structure. Especially in a so-called “system LSI (Large Scale Integration)” product in which a flash memory is merged with a high-speed logic circuit, a DRAM (Dynamic Random Access Memory), or the like, which whose market is rapidly expanding in recent years, an increase of the manufacturing cost thereof to adopt the stacked gate type memory cells are adopted for the flash memory. According to the inventors' study, this is caused by increases in the numbers of photo-masks and manufacturing steps as will be explained below. Since the tunnel oxide films of the flash memory are thicker than the gate oxide films of transistors for the logic circuit or the gate oxide films of the transistors of DRAM cells, there are required a mask for separately forming the tunnel oxide films, a mask for adding and working polysilicon films for the floating gates of the flash memory, a mask for working the word lines of the flash memory, an impurity implanting mask for forming the drain regions of the flash memory, and impurity implanting masks for forming the low-concentration N-type source and drain regions and low-concentration P-type source and drain regions of high-withstand-voltage transistors constituting write and erase circuits, and the number of the masks to be added becomes, at least, six. It is therefore difficult to provide an inexpensive system LSI for civilian goods in which a flash memory employing stacked gate type memory cells is packaged. In order to overcome this difficulty, nonvolatile memory elements of single-layer polysilicon gate structure may be formed.

[0017] It is necessary, however, to also consider the relationship of the thickness of the gate oxide films of the nonvolatile memory elements of the single-layer polysilicon gate structure with the thickness of the gate oxide films of the MIS transistors of any other circuit which is packaged together with the nonvolatile, memory elements. According to the inventors' study, the limit of the number of times of rewriting the nonvolatile memory element correlates with the thickness of the gate oxide film, and so the gate oxide film preferably should be thickened in order to moderate the rate of the deterioration of the information retention capability of the element. In order to avoid complicating the manufacturing process of a semiconductor integrated circuit, however, it is considered desirable to make the thickness of the gate oxide film in the nonvolatile memory element of the single-layer gate structure common with that of the gate oxide film of the MIS transistor of the other circuit.

[0018] An object of the present invention is to provide a semiconductor integrated circuit which can remarkably enhance a long-term information retention capability based on a memory cell including a pair of nonvolatile memory elements in a differential form.

[0019] Another object of the present invention is to simplify the device structure of a semiconductor integrated circuit in which an electrically programmable nonvolatile memory is merged and packaged.

[0020] Still another object of the present invention is to provide a semiconductor integrated circuit in which a nonvolatile memory is packaged, the nonvolatile memory being in a 2-cells/1-bit differential form adapted to conspicuously lower the rate of occurrence of readout faults without adding any new process to ordinary logic circuit processes or general DRAM processes.

[0021] Yet another object of the present invention is to provide a technique according to which flash memory cells each including a single-layer polysilicon gate are utilized as a remedy circuit for a memory module or a memory circuit formed in a semiconductor device.

[0022] The above and other objects and novel features of the present invention will become apparent from the description provided in this specification and the accompanying drawings.

[0023] Typical aspects of invention disclosed in the present application will be briefly summarized below.

[0024] [1] A first feature of the invention consists of the fact that the differential connection form of nonvolatile memory elements is adopted for the memory cell of a nonvolatile memory, and that the initial threshold voltage of the nonvolatile memory elements is determined considering the operating point of a sense amplifier and a selection voltage for a word line. More specifically, with regard to a semiconductor integrated circuit including a nonvolatile memory (113, 114 or 115) which comprises a nonvolatile memory cell (131) including a pair of nonvolatile memory elements (130) each having a source (ST3), a drain (DT3), a floating gate (FGT) and a control gate (CGT), the pair of control gates sharing a word line (WL), the pair of drains being respectively coupled to a pair of complementary data lines (DLt and DLb), and in which information items read out on said pair of complementary data lines in accordance with mutually different logical states or different threshold voltage states of said pair of nonvolatile memory elements are differentially amplified by a sense amplifier (143); a selection voltage (Vread) which is applied to said word line for the purpose of the information readout from said nonvolatile memory elements and an initial threshold voltage (Vthi) of said nonvolatile memory elements are substantially equalized to each other. By way of example, the difference voltage between both the voltages is set at a voltage (for example, a voltage of 50 mV) which is smaller than the voltage width (ÄVth) of an input voltage range within which the sense amplifier is subjected to a transient response operation (that is, the so-called “high sensitivity range” of the sense amplifier). More desirably, when the mutually different logical states of the pair of nonvolatile memory elements are determined by the relatively low threshold voltage state of one nonvolatile memory element and the relatively high threshold voltage state of the other nonvolatile memory element, the initial threshold voltage is set at a voltage which is near the average value of the relatively low threshold voltage (VthL) and the relatively high threshold voltage (VthH).

[0025] In a charge holding state, the high threshold voltage (VthH) of the nonvolatile memory element gradually approaches the initial threshold voltage (Vthi) in a thermal equilibrium state, on account of charge leakage ascribable to the electric field of the element itself as is applied to the tunnel film thereof, while the low threshold voltage (VthL) gradually approaches the initial threshold voltage (Vthi) in the thermal equilibrium state, on account of an electric field in a charge gain direction attributed to the word line selection voltage (Vread) in the readout mode. As described above, the initial threshold voltage (Vthi) and the readout word line selection voltage (Vread) are set to be substantially equal within the range of the voltage width within which the sensitivity of the sense amplifier is high. Thus, even if one nonvolatile memory element has turned faulty due to the gradual fall of the threshold voltage of the nonvolatile memory element having the high threshold voltage (VthH) or the gradual rise of the threshold voltage of the nonvolatile memory element having the low threshold voltage (VthL), the threshold voltage of the faulty memory element stops falling or rising in a state which is substantially equal to the word line selection voltage. The faulty nonvolatile memory element is therefore in the transient state or intermediate state between its ON state and its OFF state, whereby its signal state transmitted to the sense amplifier through the data line brings this sense amplifier into the input state of the transient response operation. Accordingly, if the state of the other nonvolatile memory element is normal, there is the very high possibility that the stored information of the correct logical value before the deterioration can be obtained by the differential amplification action of the sense amplifier. Thus, the capability of long-term data retention is enhanced, and a lowering of the rate of readout faults can be realized.

[0026] Especially in case of previously setting the initial threshold voltage at a voltage near the average value between the low threshold voltage and the high threshold voltage, it is possible to substantially equalize the probability of occurrence of faults ascribable to the gradual fall of the high threshold voltage (VthH) of the nonvolatile memory element and the probability of occurrence of faults ascribable to the gradual rise of the low threshold voltage (VthL) of the nonvolatile memory element, whereby the retention capability for the stored information can be enhanced to the utmost.

[0027] The nonvolatile memory element, which can be produced by a manufacturing process, such as a single-layer polysilicon process, has a MIS transistor (MFSn), and a control gate (CGT) which is disposed so as to interpose an insulating film between it and the floating gate (FGT) of the MIS transistor. The control gate is formed of an impurity-doped layer. In more detail, the source (ST3) and drain (DT3) are formed of semiconductor regions of second conductivity type which are provided in a semiconductor region (121) of first conductivity type, the floating gate is formed of a conductive layer (PSi) which is arranged over a channel defined between the source and the drain, through a gate insulating film (GO3), and the control gate is formed of a semiconductor region (122) of the second conductivity type which is arranged under the portion of the conductive layer extended from the floating gate, through the gate insulating film (GO3).

[0028] For the purpose of controlling the threshold voltages, an impurity of the first conductivity type is introduced into the floating gate of the nonvolatile memory element which can be produced by the manufacturing process such as the single-layer polysilicon process, whereby the initial threshold voltage of the nonvolatile memory element is readily set at a voltage which is approximately at the middle between the high threshold voltage and the low threshold voltage. Even in the case of introducing the impurity as stated above, a CMOS process can be applied to the manufacture of the MIS transistors for constructing the nonvolatile memory elements. In an alternative case where the threshold voltages are adjusted by the ion implantation of the first conductivity type impurity into the channel of the MIS transistor (MFsn), a photo-mask for the channel ion implantation is added to the CMOS process in the manufacture of the MIS transistors (MFSn).

[0029] The nonvolatile memory can be utilized for the storage of remedy information for remedying the defects of a volatile memory, such as a SRAM. By way of example, such an SRAM can construct a cache memory which is connected to a central processing unit. Besides, the nonvolatile storage device can construct a part or the whole of a programmable logic circuit whose stored information determines an output logical function corresponding to an input.

[0030] [2] A second feature of the invention consists in the fact that the thickness of the gate insulating films of the nonvolatile memory elements is determined considering the relationship thereof with the thickness of the gate insulating films of any other circuit. More specifically, a gate insulating film which is comparatively thick is adopted for an external interface circuit in order to enhance the electrostatic withstand voltage of an input MIS transistor whose gate is connected to an external terminal. Besides, in a semiconductor integrated circuit in which an operating supply voltage such as 3.3 V externally fed is stepped down to the operating supply voltage of an internal circuit, the MIS transistor of an external interface circuit which operates by receiving the 3.3 V has a gate oxide film which is thick as compared with that of the MIS transistor of the internal circuit, from the standpoint of enhancing the withstand voltage of the internal circuit. With notice taken of this, in a semiconductor integrated circuit (101) in which logic circuits (109, 107), nonvolatile memories (113, 114, 115) and an external interface circuit (103) are merged and packaged on a semiconductor substrate, the gate insulating films (GO3) of the MIS transistors (MFSn) for constructing the nonvolatile memory elements which can be produced by the manufacturing process such as the single-layer polysilicon process are equalized in thickness within the allowable range of errors ascribable to process deviations, to the gate insulating films (GO1) of the MIS transistors (MIOn) included in the external interface circuit. In other words, the gate insulating films of the MIS transistors for constructing the nonvolatile memory elements and those of the MIS transistors included in the external interface circuit are simultaneously fabricated by utilizing an identical process or a common photo-mask. In this manner, the thickness of the gate oxide films in the nonvolatile memory elements of the single-layer gate structure is made common with the thicknesses of the gate oxide films of the MIS transistors of the other circuits, whereby the nonvolatile memory elements (130) can be endowed with a somewhat long information retention capability while preferentially avoiding any complication of the manufacturing process of the semiconductor integrated circuit.

[0031] In a case where a satisfactory information retention capability cannot be ensured in point of the gate insulating film thickness when equalizing the gate insulating film thickness of the nonvolatile memory elements to that of the MIS transistors of the external interface circuit as explained above, the memory cell (131) in which the nonvolatile memory elements (130) are connected in the differential form can be adopted. Further, the information retention capability can be enhanced still more in such a way that, as described in connection with the first feature, the initial threshold voltage of the nonvolatile memory elements is determined in relation to the sensitivity of the sense amplifier and the word line selection voltage and also in relation to the high threshold voltage and low threshold voltage of the nonvolatile memory elements.

[0032] Further, when notice is taken of the other circuits which are merged and packaged in the semiconductor integrated circuit including the nonvolatile memories, the thickness of the gate insulating films of the MIS transistors of the nonvolatile memory elements can be equalized to that of the gate insulating films of the MIS transistors included in the DRAM. In addition, the gate insulating films of the MIS transistors for constructing the nonvolatile memory elements are formed to be thicker than those of the MIS transistors included in the logic circuit.

[0033] When notice is taken of the fact that the nonvolatile memory elements can be formed using the manufacturing process, such as the single-layer polysilicon process, the floating gates of the MIS transistors constructing the nonvolatile memory elements, the gates of the MIS transistors included in the logic circuit, the gates of the MIS transistors included in the input/output circuit, and the gates of the MIS transistors included in the DRAM may be formed to have equal film thicknesses within the allowable range of errors ascribable to process deviations. That is, even with the single-layer polysilicon process or the like single-layer gate process, it is possible to obtain a semiconductor integrated circuit, such as a system LSI in which a DRAM formed of the nonvolatile memory having an excellent data retention capability, etc. is simultaneously merged and packaged.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034]FIG. 1 is diagram schematically showing the sectional structures of the nonvolatile memory elements of flash memories and MIS transistors of n-channel type included in an external input/output circuit as well as a logic circuit, the memories and the circuits being merged in a system LSI which is an example of a semiconductor integrated circuit according to the present invention;

[0035]FIG. 2 is a schematic chip plan diagram of the system LSI which is an example of the semiconductor integrated circuit according to the present invention;

[0036]FIG. 3 is a diagram showing the erase operation state of the nonvolatile memory element shown in FIG. 1;

[0037]FIG. 4 is a diagram showing the write operation state of the nonvolatile memory element shown in FIG. 1;

[0038]FIG. 5 is a diagram showing the readout operation of the nonvolatile memory element shown in FIG. 1;

[0039]FIG. 6 is a circuit diagram showing an example of a memory cell which is configured of a pair of nonvolatile memory elements in a differential form;

[0040]FIG. 7 is a plan layout view of the memory cells in FIG. 6, depicted in device structure fashion;

[0041]FIG. 8 is a schematic diagram of a flash memory which employs memory cells of differential connection form;

[0042]FIG. 9 is a circuit diagram showing a practical example of a sense amplifier which is provided in the flash memory in FIG. 8;

[0043]FIG. 10 is a graph relevant to the threshold voltage distribution of the nonvolatile memory elements, showing the relationship between an initial threshold voltage and a word line selection voltage;

[0044]FIG. 11 is a graph showing an example of the input/output characteristics of the sense amplifier;

[0045]FIG. 12 is a graph showing the threshold voltage distribution of a memory cell in the case where an initial threshold voltage is set comparatively high;

[0046]FIG. 13 is a graph showing the threshold voltage distribution of a memory cell in the case where an initial threshold voltage is set comparatively low;

[0047]FIG. 14 is graph showing the actual measurement values of the rate f of the faulty bits of retention faults for different thicknesses of tunnel films, the values being used for computing the effect of improving the rate of chip faults;

[0048]FIG. 15 is a graph showing results obtained by comparing the rates of chip faults in the present invention and a 1-cell/1-bit scheme in the related art;

[0049]FIG. 16 is a graph showing results obtained by comparing the rate of chip faults of a flash memory of 64 kB which adopts the memory cells of the differential form configured of the nonvolatile memory elements in FIG. 1, with that in the related art 1-cell/1-bit scheme;

[0050]FIG. 17 is a vertical sectional view of the essential portions of a device during a process step for manufacturing the memory cell of the flash memory and the MIS transistor of the logic circuit in FIG. 1;

[0051]FIG. 18 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 17;

[0052]FIG. 19 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 18;

[0053]FIG. 20 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 19;

[0054]FIG. 21 is a vertical sectional view of the essential portions of a device during a process step for manufacturing the system LSI in FIG. 2, in a case where gate oxide films have two sorts of thicknesses and where a CMOS process adopting single-layer polysilicon gates is employed;

[0055]FIG. 22 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 21;

[0056]FIG. 23 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 22;

[0057]FIG. 24 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 23;

[0058]FIG. 25 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 24;

[0059]FIG. 26 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 25;

[0060]FIG. 27 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 26;

[0061]FIG. 28 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 27;

[0062]FIG. 29 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 28;

[0063]FIG. 30 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 29;

[0064]FIG. 31 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 30;

[0065]FIG. 32 is a vertical sectional view of the essential portions of the device during manufacturing steps subsequent to the process step in FIG. 31;

[0066]FIG. 33 is a block diagram of a microcomputer which represents a second example of the semiconductor integrated circuit according to the present invention; and

[0067]FIG. 34 is a block diagram showing a detailed example in the case where an SRAM in FIG. 33 is provided as a cache memory.

DESCRIPTION OF THE PREFERRED EMBODIMENTS System LSI

[0068] Schematically shown in FIG. 2 is a chip plan view of a system LSI which represents an example of a semiconductor integrated circuit according to the present invention. Although the invention is not especially restricted thereto, the system LSI 101 illustrated in the figure is so constructed that a large number of external connection electrodes, such as bonding pads, 102 are arranged at the peripheral edge of a semiconductor substrate 100, and that an external input/output circuit 103 and an analog input/output circuit 104 are disposed inside the electrodes 102. The external input/output circuit 103 and the analog input/output circuit 104 have an operating supply voltage which is an external supply voltage of relatively high level, such as 3.3 V. A level shifter 105 steps down the external supply voltage to an internal supply village such as 1.8 V. Inside the level shifter 105, there are a dynamic random access memory (DRAM) 106, a central processing unit (CPU) 107, a cache memory (CACH) 108, a logic circuit (LOG) 109, a phase-locked loop circuit (PLL) 110, an analog-to-digital conversion circuit (ADC) 111, and a digital-to-analog conversion circuit (DAC) 112. Indicated at numerals 113 to 115 are electrically erasable and programmable nonvolatile memories, for example, flash memories, respectively. The DRAM 106, CPU 107, LOG 109 and CACH 108 are operated by their operating supply voltage which is the internal supply voltage, such as 1.8 V, fed from the level shifter 105. The DRAM 106, however, steps up the internal supply voltage so as to form a word line selection level, which is used as the operating supply voltage of a word driver etc. Each of the flash memories 13 to 15 is operated with the internal supply voltage in a data readout operation, but it requires a high voltage in erase and write operations. The high voltage may be formed by an internal booster circuit, or may well be fed from outside and through a predetermined external connection electrode in the predetermined operating mode of the system LSI, such as the EPROM writer mode thereof to be described later.

[0069] The flash memory 113 is utilized for storing the remedy information (control information for replacing faulty memory cells with redundant memory cells) of the DRAM 106, while the flash memory 114 is utilized for storing the remedy information of the cache memory 108 and is packaged instead of a remedying program circuit based on the use of fuses. The flash memory 115 constitutes a programmable logic circuit whose stored information determines the logical function of an output n response to an input. By way of example, the flash memory 115 functions as a logic circuit in which results each having been obtained by executing a predetermined logical operation for the plurality of bits of an address signal are held as data beforehand, so as to deliver a predetermined logical operation result corresponding to the combination of the logical values of address input signals

[0070] Although the invention is not especially restricted thereto, the system LSI 101 includes complementary MIS transistors (insulated-gate field effect transistors) which are formed on a single semiconductor substrate such as single-crystal silicon by single-layer polysilicon gate processes, and whose gate oxide films have two sorts of thicknesses. 

39. A semiconductor integrated circuit comprising: a logic circuit, a nonvolatile memory and an external interface circuit merged and packaged on a semiconductor substrate, wherein said nonvolatile memory comprises a nonvolatile memory element which is constructed so as to be electrically programmable by a MIS transistor and a control gate; said MIS transistor having a source and a drain of second conductivity type formed in a semiconductor region of a first conductivity type, a gate insulating film formed on a channel formed under an extension portion of said floating gate through a gate insulating film; and a gate insulating film of said MIS transistor constituting said nonvolatile memory element, and a gate insulating film of a MIS transistor included in said external interface circuit have substantially equal thicknesses.
 40. A semiconductor integrated circuit, comprising: a logic circuit, a nonvolatile memory and an external interface circuit included on a semiconductor substrate, wherein: said nonvolatile memory comprises a nonvolatile memory cell which includes a pair of nonvolatile memory elements each being constructed so as to be electrically programmable by a MIS transistor and a control gate; said MIS transistor being formed with a source and a drain of a second conductivity type in a semiconductor region of a first conductivity type, and a floating gate over a channel defined between said source and said drain, through a gate insulating film; said control gate being made of a semiconductor region of the second conductivity type formed under an extension portion of said floating gate through a gate insulating film; and in which the pair of control gates are connected in common to a word line, while drains of the pair of transistors are coupled to a pair of complementary data lines; said nonvolatile memory being so operated that information items read out on said pair of complementary data lines in accordance with mutually different threshold voltage states of said pair of nonvolatile memory elements are differentially amplified by a sense amplifier; a difference voltage between a selection voltage which is applied to said word line for the purpose of the information readout from said nonvolatile memory elements and an initial threshold voltage of said MIS transistors constituting said nonvolatile memory elements is a voltage smaller than a voltage width of an input voltage range within which said sense amplifier is subjected to a transient response operation; and the gate insulating films of said MIS transistors constituting said nonvolatile memory elements; and a gate insulating film of a MIS transistor included in said external interface circuit have substantially equal thicknesses.
 41. A semiconductor integrated circuit according to claim 40, wherein: the mutually different threshold voltage states of said pair of nonvolatile memory elements are determined by a relatively low threshold voltage state of one of said nonvolatile memory elements and a relatively high threshold voltage state of the other one of said nonvolatile memory elements; and the initial threshold voltage is a voltage which is near an average value between the relatively low threshold voltage and the relatively high threshold voltage.
 42. A semiconductor integrated circuit according to claim 41, wherein a DRAM is further included on said semiconductor substrate, and that a gate insulating film of a MIS transistor included in said DRAM and said gate insulating film of said MIS transistor included in said external interface circuit have substantially equal thicknesses.
 43. A semiconductor integrated circuit according to claim 42, wherein the thicknesses of said gate insulating films are substantially equal within an allowable range based on process deviations.
 44. A semiconductor integrated circuit according to claim 41, wherein the gate insulating films of said MIS transistors constituting said nonvolatile memory elements are formed to be thicker than a gate insulating film of a MIS transistor included in said logic circuit.
 45. A semiconductor integrated circuit according to claim 41, wherein the floating gates of said MIS transistors constituting said nonvolatile memory elements, a gate of a MIS transistor included in said logic circuit, and a gate of said MIS transistor included in the input/output circuit are formed at substantially equal film thicknesses.
 46. A semiconductor integrated circuit according to claim 42, wherein the floating gates of said MIS transistors constituting said nonvolatile memory elements, a gate of a MIS transistor included in said logic circuit, a gate of said MIS transistor included in the input/output circuit, and a gate of said MIS transistor included in said DRAM are formed at substantially equal film thicknesses.
 47. A semiconductor integrated circuit according to claim 46, wherein the thicknesses of said gate insulating films a substantially equal within an allowable range based on process deviations.
 48. A semiconductor integrated circuit comprising: a logic circuit, a nonvolatile memory and an external interface circuit included on a semiconductor substrate, wherein: said nonvolatile memory comprises a nonvolatile memory element which is constructed so as to be electrically programmable by a MIS transistor and a control gate; said MIS transistor being formed with a source and a drain of a second conductivity type in a semiconductor region of a first conductivity type, and a floating gate over a channel defined between said source and said drain, through a gate insulating film; said control gate being made of a semiconductor region of the second conductivity type formed under an extension portion of said floating gate through a gate insulating film; and said gate insulating film of said MIS transistor constituting said nonvolatile memory element is formed to be thicker than a gate insulating film of a MIS transistor included in said logic circuit.
 49. A semiconductor integrated circuit comprising: a logic circuit, a nonvolatile memory and an external interface circuit formed on a semiconductor substrate, wherein: said nonvolatile memory comprises a nonvolatile memory cell which includes a pair of nonvolatile memory elements each being constructed so as to be electrically programmable by a MIS transistor and a control gate; said MIS transistor being formed with a source and a drain of a second conductivity type in a semiconductor region of a first conductivity type, and a floating gate over a channel defined between said source and said drain, through a gate insulating film; said control gate being made of a semiconductor region of the second conductivity type formed under an extension portion of said floating gate through a gate insulating film; and in which the pair of control gates are connected in common to a word line, while drains of the pair of MIS transistors are coupled to a pair of complementary data lines; said nonvolatile memory being so operated that information items read out from the nonvolatile memory cell onto said pair of complementary data lines in accordance with mutually different threshold voltage states of said pair of nonvolatile memory elements are differentially amplified by a sense amplifier; a difference voltage between a selection voltage which is applied to said word line for the purpose of the information readout from said nonvolatile memory elements and an initial threshold voltage of said MIS transistors included in said nonvolatile memory elements is a voltage smaller than a voltage width of an input voltage range within which said sense amplifier is subjected to a transient response operation; and the gate insulating films of said MIS transistors constituting said nonvolatile memory elements are formed to be thicker than a gate insulating film of a MIS transistor included in said logic circuit.
 50. A semiconductor integrated circuit according to claim 49, wherein: the mutually different threshold voltage states of said pair of nonvolatile memory elements are determined by a relatively low threshold voltage state of one of said nonvolatile memory elements and a relatively high threshold voltage state of the other one of said nonvolatile memory elements; and the initial threshold voltage is a voltage which is near an average value between the relatively low threshold voltage and the relatively high threshold voltage.
 51. A semiconductor integrated circuit according to claim 50, wherein a DRAM is further included on said semiconductor substrate, and that a gate insulating film of a MIS transistor included in said DRAM has a thickness equal within an allowable range based on process deviations, to that of said gate insulating films of said MIS transistors constituting said nonvolatile memory elements.
 52. A semiconductor integrated circuit according to claim 51, wherein the allowable range of the gate insulating film thicknesses based on the process deviations is approximately ±0.5 nm relative to a target film thickness.
 53. A semiconductor integrated circuit according to claim 50, wherein the floating gates of said MIS transistors constituting said nonvolatile memory elements, a gate of a MIS transistor included in said logic circuit, and a gate of a MIS transistor included in the input/output circuit are formed at film thicknesses equal within an allowable range based on process deviations.
 54. A semiconductor integrated circuit according to claim 52, wherein the floating gates of said MIS transistors constituting said nonvolatile memory elements, a gate of said MIS transistor included in said logic circuit, a gate of a MIS transistor included in the input/output circuit, and a gate of said MIS transistor included in said DRAM are formed at film thicknesses equal within an allowable range based on process deviations.
 55. A semiconductor integrated circuit according to claim 54, wherein the allowable range of the gate film thicknesses based on the process deviations is approximately ±10% relative to a target film thickness.
 56. A semiconductor integrated circuit according to claim 50, further comprising: a volatile storage circuit in which control information read out of said nonvolatile memory is stored; and is a volatile memory which includes a plurality of first volatile memory cells and second volatile memory cells and in which the first volatile memory cell is replaced with the second volatile memory cell in accordance with the control information transferred to said volatile storage circuit.
 57. A semiconductor integrated circuit according to claim 56, wherein said volatile memory is a cache memory connected to said logic circuit.
 58. A semiconductor integrated circuit according to claim 50, wherein said nonvolatile memory constructs a programmable logic-circuit whose stored information determines an output logical function corresponding to an input. 